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<string language="el">Scalable FPGA accelerator of the NRM algorithm for efficient stochastic simulation of large-scale biochemical reaction networks</string>
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<entry>http://hdl.handle.net/10795/1981</entry>
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<string language="el">βιοχημεία</string>
<string language="el">προσομοίωση</string>
<string language="el">πληροφορική</string>
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<string language="el">Stochastic simulation of large-scale biochemical reaction networks, with thousands of reactions, is important for systems biology and medicine since it will enable the insilico experimentation with genome-scale reconstructed networks. FPGA based stochastic simulation accelerators can exploit parallelism, but have been limited on the size of biomodels they can handle. We present a high performance scalable System on Chip architecture for implementing Gibson and Bruck's Next Reaction Method efficiently in reconfigurable hardware. Our MPSoC uses aggressive pipelining at the core level and also combines many cores into a Network on Chip to also execute in parallel stochastic repetitions of complex biomodels, each one with up to 4K reactions. The performance of our NRM core depends only on the average outdegree of the biomodel's Dependencies Graph (DG) and not on the number of DG nodes (reactions). By adding cores to the NoC, the system's performance scales linearly and reaches GCycles/sec levels. We show that a medium size FPGA running at ~200 MHz deliver high speedup gains relative to a popular and efficient software simulator running on a very powerful workstation PC.</string>
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<string language="el">8 pp.</string>
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FN: Koutsouradis, Evangelos
N: Koutsouradis, Evangelos
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FN: Μανωλάκος, Ηλίας
N: Μανωλάκος, Ηλίας
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FN: Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών
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<date>
<dateStamp>2015-08</dateStamp>
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<string language="el">Systems Biology</string>
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<keyword>
<string language="el">Stochastic Simulation</string>
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<string language="el">Biochemical Reaction Networks</string>
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<string language="el">Next Reaction Method</string>
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<string language="el">SoC</string>
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<string language="el">FPGA</string>
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<string language="el">VHDL</string>
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<string language="el">Parallel Processing</string>
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<string language="el">Pipelining</string>
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<location>DOI:     10.1109/DSD.2015.53</location>
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<location>http://repository.edulll.gr/edulll/bitstream/10795/1981/2/1981_StochSoCs_3828_NRM_Paper_DSD_2015.pdf</location>
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FN:National Documentation Centre - National Hellenic Research Foundation
N:National Documentation Centre - National Hellenic Research Foundation
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<date><dateTime>2016-02-17T13:36:01Z</dateTime></date>
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